1. Field of the Invention
This invention relates to a method and apparatus for performing multiply operation of floating point data in 2-cycle pipeline scheme, and more particularly to a method and apparatus for processing multiply operation used in designing a floating point processor in microprocessor. The floating point data processing of a multiplier can be used widely to design microcontrollers or graphics controllers as well as microprocessors.
2. Description of the Related Art
Generally, multiply operation of floating point data requires a lot of hardware basic cells, i.e. adders. One of the conventional solutions to this is reducing the size of the basic cell or optimizing the structure for higher operating speed. However, these and other conventional solutions are not intended to reduce the number of the used basic cells. Therefore, the areal problem resulted from using so many basic cells still needs to be solved.